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5.5 Interrupt Mode Control Register (Base + 6)

The mode of both the external interrupt and the Port C interrupts may be controlled with the

Interrupt Mode Control Register. The upper nibble (4 bits) and lower nibble (4 bits) of the

Port C interrupts may be configured separately. The external interrupt may also be enabled by

writing this register. The status of the external interrupt may be read in this register and the

external interrupt may also be acknowledged by writing the appropriate bit in the Interrupt

Mode Control Register.

These two bits control the mode of the Lower Nibble of

Port C(INT3, INT2, INT1, INT0):

00 = Level Sensitive Active Low Interrupt

01 = Level Sensitive Active High Interrupt

10 = High-to-low Transition Edge Sensitive Interrupt

11 = Low-to-high Transition Edge Sensitive Interrupt

LowerIntCntrl

1:0

These two bits control the mode of the Upper Nibble of

Port C (INT7, INT6, INT5, INT4):

00 = Level Sensitive Active Low Interrupt

01 = Level Sensitive Active High Interrupt

10 = High-to-low Transition Edge Sensitive Interrupt

11 = Low-to-high Transition Edge Sensitive Interrupt

UpperIntCntrl

3:2

These two bits control the mode of the external

interrupt:

00 = Level Sensitive Active Low Interrupt

01 = Level Sensitive Active High Interrupt

10 = High-to-low Transition Edge Sensitive Interrupt

11 = Low-to-high Transition Edge Sensitive Interrupt

ExtIntControl

5:4

1 = external interrupt is enabled

0 = external interrupt is disabled

ExtraIntEn

ExtIntStat: to read status of external interrupt

ExtIntAck: write acknowledges external interrupt

ExtIntStat(Read)

ExtIntAck(Write)

DescriptionNameBit

Table 5-6. Interrupt Mode Control Register

5.6 Interrupt Status Register (Read Only) (Base + 7)

On a read, this register provides the interrupt status for the Port C interrupts. This provides a

mechanism for determining the sources of any pending interrupts. A '1' signals that an

interrupt generating condition has occurred on the appropriate channel. Interrupts will

continue to occur until this register has a value of 00h and no interrupt generating conditions

remain. This register must be 'reset' by acknowledging interrupts via writing the Interrupt

Acknowledge Register.

The Status of INT7 - INT0 is read

(Bit 7 = INT7, Bit 6 = INT6, etc...)

ChanCIntStatus

7:0

DescriptionNameBit

Table 5-7. Interrupt Status Register (Read Only)

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